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ESS Technology, Inc.
DESCRIPTION
The ESS Technology ES2898/ES2828 TeleDrive chipset is a highly integrated solution that brings advanced modem functionality to notebooks, desktops, and add-incards. The ES2898/ES2828 chipset provides an efficient 56k (V.90) data/fax solution and adds both a telephone answering machine (TAM) feature and a full-duplex speakerphone feature. The data pump algorithms run on the ES2898 DSP, along with the echo cancellation required for implementing a fullduplex speakerphone feature. The host CPU is utilized to run the modem controller functions, including the standard AT command set, V.42bis data compression features, Classes 1 and 2 fax, and ITU-T V.80 sync access to support H.324 video conferencing applications. The ES2898 DSP offers an integrated PCI bus interface. The ES2828 is the companion analog-front-end (AFE) chip to the ES2898. It integrates a low-pass, continuoustime anti-aliasing filter, a 16-bit resolution ADC, a 16-bit DAC, a low-pass output-reconstruction filter, and a CHI bus interface to interface to the ES2898. The ES2828 includes two signal processing channels that operate synchronously so that data reception at the ADC channel and data transmission from the DAC channel occur during the same time interval. The ES2828 also incorporates an AC-Link to interface to core logic chipsets to provide a standalone MC`97 host-based V.90/V.92 modem solution. The ES2898 DSP is available in an industry-standard 100pin low-profile quad flat pack (LQFP) package. The ES2828 is available in an industry-standard 48-pin lowprofile quad flat pack (LQFP) package.
(R)
ES2898/ES2828 V.90 PCI DSP Modem Solution Product Brief
MODEM FEATURES
* Data mode capabilities:
--- --- --- --- --- --- --- --- --- --- --- V.90 56 kbps V.34 33.6 kbps and fallbacks Standard AT command set V.42 (LAPM) and MNP error correction V.42bis/MNP 5 data compression 3.3V power supply, 5V input tolerant ITU-T V.17, V.21 ch2, V.27ter, and V.29 Group 3 (TIA/EIA 578 Class 1 and Class 2) Telephone answering machine Full duplex speakerphone Caller ID
* Fax mode capabilities:
* Telephony capabilities:
* Sigma-delta modulation codec * Programmable downsampling frequency for modem and
voice applications
* * * * *
ACPI power management support TIES escape sequence V.80 (H.324 software stack compatible) Fully ACPI-compliant Microsoft WindowsTM 98/SE/ME/2000: --- --- UNIMODEM V TAPI
* Microsoft Windows NT 4.0
SYSTEM BLOCK DIAGRAM
Figure 1 Shows the ES2898/ES2828 system block diagram.
CHI BUS I/F
PCI BUS INTERFACE
ES2898 TeleDrive
4
ES2828 Modem AFE
DAA
18.816 MHz
Figure 1 ES2898/ES2828 System Block Diagram
ESS Technology, Inc.
SAM0402-050301
1
ES2898/ES2828 PRODUCT BRIEF PINOUT
PINOUT
Figure 2 shows the ES2898 and ES2828 pinout diagrams.
DR0 TFS0 RFS0 SCLK0 GND DT1 DR1 TFS1 RFS1 SCLK1 NC NC NC SEDO BSEL0 VDD(5V) PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 FL2
SDATA_IN PWDN# XTALO XTALI DVDD RST# CKO ID0 ID1
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VAUX GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 DGND GPIO_6 GPIO_7 GPIO_8 GPIO_9
37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12
SO
SC
FS
DPBX
DVDD
AGND
AGND
AGND
Figure 2 ES2898 and ES2828 Pinout Diagrams
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SAM0402-050301
ACLINK/GPIO_B
RXIN+
RXIN-
AVDD
AUX+
AUX-
VCM
AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 GND CBE3# VDD VDD VDD NC GND CBE2# GND AD15 AD14 AD13
SI DVDD CTST DGND HCT VCMX AGND TXTX+ VRBP VREF VCBP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
DT0 VDD TEST/PF9 RING_IN VAUX PME# VAUXP VDD PCI CLK VDD INTA PAR RST# FRAME# GND IRDY# STOP# VDD DAA_PM TRDY# IDSEL DEVSEL# AD31 AD30 AD29
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
ES2898S 100-Pin LQFP
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
FL1 FL0 VDD GND VDD BSEL1 CLKOUT XTALO XTALI GND AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 CBE0# CBE1# AD8 AD9 AD10 AD11 AD12
ES2828S 48-PIN LQFP
20 19 18 17 16 15 14 13
ESS Technology, Inc.
ES2898/ES2828 PRODUCT BRIEF PIN DESCRIPTIONS
PIN DESCRIPTIONS
Table 1 lists the ES2898 pin descriptions. Table 2 lists the ES2828 pin descriptions. Table 1 ES2898 Pin Descriptions
Names AD[16:31] GND C/BE[3:0]# 15, 21, 31, 32 VDD VDD PERR# AD[0:15] XTALI 16, 18, 46, 48, 77, 83, 85, 93 17 19 23:30, 33:40 42 I I Pin Numbers 1:13, 98, 99, 100 14, 20, 22, 41, 47, 71, 90 I/O I -- Definitions When the ES2898 interfaces a PCI bus, these pins function as AD[16:31]. The PCI bus implements a 32-bit multiplexed address and data bus. Ground. Bus command/byte enable. These pins are multiplexed. During the address phase of a bus transaction, these pins define the bus command. During the data phase, these pins are used as byte enables. Digital supply voltage, 3.3V. When the ES2898 interfaces a PCI bus, use an internal chip select and tie the CS pin to this VDD pin through a pullup 10k resistor. Parity error output. When the ES2898 interfaces a PCI bus, these pins function as AD[15:0]. The PCI bus implements a 32-bit multiplexed address and data bus. ES2898 clock input. This pin can be driven by either a crystal or an oscillator. When using a crystal, XTALO is used as the other crystal pin. When using an oscillator, the output of the oscillator is connected to XTALI. An internal clock doubler doubles the frequency at XTALI. Works in conjunction with XTALI when a crystal is used. When an oscillator is used, XTALO is left unconnected. Fixed-frequency clock output. The frequency of this pin is the same as the crystal input of the DSP clock. The clock is stopped during D2 and D3 states when the ST_CLKOUT bit is set. Used to determine the operating mode of the ES2898. These pins are sampled at the falling edge of reset and are encoded as follows:.
Configuration Reserved Reserved PCI interface Generic 16-bit host interface BSEL1 (pin 45) 0 0 1 1 BSEL0 (pin 61) 0 1 0 1
I O I/O I
XTALO CLKOUT BSEL1 / BSEL0
43 44 45, 61
O O I
FL0 FL1 FL2
49 50 51
O O O
Used as flag 0 output during normal operation. Used as flag 1 output during normal operation while the bypass circuitry is included. Will be activated during power-down mode. Functions as flag 2 output during normal operation, and can also be used to provide a passthrough reset to the ES2828. To bring the devices out of reset, write a logic zero. FL2 carries the reset signal for the ES2828. General-purpose programmable bidirectional flag pins. These pins can be used for interfacing with a telephone or other device, performing such functions as phone-off-hook, phone-on-hook, ring, caller ID, etc. PF[0] is specially designed to support the ring function. Digital supply voltage. If the ES2898 interfaces with a 5V input, tie this pin to 5V. Otherwise, tie this pin to 3.3V. Serial EEPROM data input. Serial EEPROM chip select. Serial EEPROM serial data output. Serial EEPROM clock. One of two serial clock inputs. This clock can be generated either by the ES2898 or by the ES2828.
PF[7:0]
52, 53, 54, 55, 56, 57, 58, 59 60 62 63 64 65 66
I/O
VDD(5V) SEDO SECS SEDI SECLK SCLK1
I I O O O I/O
ESS Technology, Inc.
SAM0402-050301
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ES2898/ES2828 PRODUCT BRIEF PIN DESCRIPTIONS
Table 1 ES2898 Pin Descriptions (Continued)
Names RFS1 TFS1 DR1 DT1 SCLK0 RFS0 TFS0 DR0 DT0 TEST / PF9 RING_IN VAUX PME# VAUXP Pin Numbers 67 68 69 70 72 73 74 75 76 78 79 80 81 82 84 86 87 I/O I/O I/O I O I/O I/O I/O I O I I I O I I O I/O Definitions Receive frame for serial port 1. Can be generated either internally or externally. This signal is asserted one clock before data is sent on the DR1 pin. Transmit frame for serial port 1. Can be generated either internally or externally. Data receive pin for serial port 1. Data transmit pin for serial port 1. One of two serial clock inputs. This clock can be generated either by the ES2898 or by the ES2828. Receive frame for serial port 0. Can be generated either internally or externally. This signal is asserted one clock before data is sent on the DR0 pin. Transmit frame for serial port 0. Can be generated either internally or externally. Data receive pin for serial port 0. Data transmit pin for serial port 0. Used during device test. Tie this pin to ground through a 4.7k resistor. Used for ring detect input during the D3cold state to drive the device back to its default power-up state. Power to device during implementation of the D3cold state required by PCI Power Management Interface specification. PME# output. VAUX support detection input. VAUXP pin is driven high to indicate that ACPI is supported with D3cold state. No support when driven low. PCI bus input clock. Functions as PCI CLK pin and operates at 33 MHz. Interrupt A. Used to request an interrupt from the PCI bus. Parity pin. PAR is stable and valid one clock after the address phase. For data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. Cycle frame. FRAME# is driven by the current master to indicate the beginning and duration of an access. FRAME# is asserted to indicate the start of a bus transaction. When FRAME# is deasserted, the transaction is in the final data phase or has been completed. Initiator ready. IRDY# is used in conjuction with TRDY# and indicates the bus master's ability to complete the current data phase of a transaction. During a write transaction, IRDY# indicates that valid data is present on AD[16:31] and AD[0:15]. During a read transaction, IRDY# indicates that master is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. Stop. STOP# indicates the current target is requesting the master to stop the current transaction. Target ready. TRDY# is used in conjuction with IRDY# and indicates the bus master's ability to complete the current data phase of a transaction. During a write transaction, TRDY# indicates that valid data is present on AD[16:31] and AD[0:15]. During a read transaction, TRDY# indicates that master is prepared to accept data. Wait cycles are inserted until both TRDY# and IRDY# are asserted together. Initialization device select. IDSEL is used as a chip select during configuration read and write transactions. Device select. When actively driven, DEVSEL# indicates that the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. Active-low ES2898 reset input. DAA power control output.
CLK INTA# PAR
FRAME#
89
I/O
IRDY#
91
I/O
STOP# TRDY#
92 95
I/O O
IDSEL DEVSEL#
96 97
O O
RESET# DAA_PM
88 94
I O
4
SAM0402-050301
ESS Technology, Inc.
ES2898/ES2828 PRODUCT BRIEF
Table 2 ES2828 Pin Descriptions
Names DPBX ACLINK/GPIO_B DVDD AGND AUX+ AUXRXIN+ RXINAVDD VCM VCBP VREF VRBP TX+ Pin Numbers 1 2 3, 23, 29 4:6, 18 7 8 9 10 11 12 13 14 15 16 I/O I I/O P I I I I I I O I O I O Digital PBX detection. Default for CHI bus mode (internal pulldown). Pull high for AC-Link mode. 3.3V digital power. Analog ground. Codec analog auxiliary differential positive input. The DC level is Vcm, and the full-scale input is either 0.22 Vp-p 5% or 1.1 Vp-p5%, depending on the gain setting. Codec analog auxiliary differential negative input. The DC level is Vcm, and the full-scale input is either 0.22 Vp-p 5% or 1.1 Vp-p5%, depending on the gain setting. Codec analog differential positive input. The DC level is Vcm, and the full-scale input is either 0.22 Vp-p 5% or 1.1 Vp-p5%, depending on the gain setting. Codec analog differential negative input. The DC level is Vcm, and the full-scale input is either 0.22 Vp-p 5% or 1.1 Vp-p5%, depending on the gain setting. Analog 5.0V supply. Common mode voltage bypass 1. Has a range of 2.16V5%. Bypass to VCBP with 0.1-F ceramic chip capacitor parallel with 10-F tantalum capacitor. Ground pin for VCM. Voltage reference bypass. Has a range of 1.2356V5%. Bypass to VRBP with 0.1-F ceramic chip capacitor parallel with 10-F tantalum capacitor. Ground pin for VREF. Codec positive analog output. The DC level is Vcm, and the full-scale ac output is either 2.8V p-p5% or 1.4V p-p5%, depending on the gain setting. The maximum loading is 1k , in parallel with 20 pF for modem applications. For audio applications with low-impedance load, the maximum distortion-free (THD <-60 db) current is 10 mA rms. Codec negative analog output. The DC level is Vcm, and the full-scale ac output is either 2.8V p-p5% or 1.4V p-p5%, depending on the gain setting. The maximum loading is 1k , in parallel with 20 pF for modem applications. For audio applications with low-impedance load, the maximum distortion-free (THD <-60 db) current is 10 mA rms. Codec common mode reference voltage output. 2.16V5%, maximum current 500 A, maximum capacitive load 20 pF. Codec digital input mode control. Digital ground. Codec sigma delta modulator test port output enable. Serial port input (default). Serial port output without VAUX support. Serial port clock output. While input must be TTL-compatible, should be able to handle 3.3V input. Serial port frame sync. 3.3V clock output. 24.576-MHz crystal oscillator output. 24.576-MHz crystal oscillator input. Reset. Definitions
TX-
17
O
VCMX HCT DGND CTST SI SO SC FS CKO XTALO XTALI RST#
19 20 21, 44 22 24 25 26 27 28 30 31 32
O I P I I O I/O O O O I I
ESS Technology, Inc.
SAM0402-050301
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ES2898/ES2828 PRODUCT BRIEF ORDERING INFORMATION
Table 2 ES2828 Pin Descriptions (Continued)
Names ID1 PWDN# ID0 SDATA_IN VAUX GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 Pin Numbers 33 34 35 36 37 I/O I I I O I Definitions Modem AFE configuration strap pin 1. When pulled down internally with ID0 pin 35, helps set primary and secondary modem codec ID configuration. Power down. Modem AFE configuration strap pin 0. When pulled down internally with ID1 pin 33, helps set primary and secondary modem codec ID configuration. Serial port output with VAUX support. Power to device during implementation of the D3cold state required by PCI power management Interface specification. GPIO_0 input/output. GPIO_1 input/output. Used for voice relay control pin (output). GPIO_3 input/output. GPIO_4 input/output. GPIO_5 input/output. GPIO_6 input/output. GPIO_7 input/output. GPIO_8 input/output. GPIO_9 input/output.
38 39 40 41 42 43 45 46 47 48
I I/O I/O I/O I/O I/O I/O I/O I/O I/O
ORDERING INFORMATION
Part Numbers ES2898S ES2828S Descriptions V.90 PCI DSP Modem Modem Analog Front End Packages 100-pin LQFP 48-pin LQFP
ESS Technology, Inc. 48401 Fremont Blvd. Fremont, CA 94538 Tel: (510) 492-1088 Fax: (510) 492-1898
6
No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are subject to change without prior notice.
ESS Technology, Inc. assumes no responsibility for any errors contained herein. TeleDrive is a registered trademark of ESS Technology, Inc. (P) U.S. patents pending. All other trademarks are owned by their respective holders and are used for identification purposes only.
(c) 2001 ESS Technology, Inc.
SAM0402-050301

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